Steep-slope vertical-transport transistors built from sub-5 nm Thin van der Waals heterostructures
Qiyu Yang, Zheng‐Dong Luo, Huali Duan, Xuetao Gan, Dawei Zhang, Yuewen Li, Dongxin Tan, Jan Seidel, Wenchao Chen, Yan Liu, Yue Hao, Genquan Han
Abstract
Abstract Two-dimensional (2D) semiconductor-based vertical-transport field-effect transistors (VTFETs) – in which the current flows perpendicularly to the substrate surface direction – are in the drive to surmount the stringent downscaling constraints faced by the conventional planar FETs. However, low-power device operation with a sub-60 mV/dec subthreshold swing (SS) at room temperature along with an ultra-scaled channel length remains challenging for 2D semiconductor-based VTFETs. Here, we report steep-slope VTFETs that combine a gate-controllable van der Waals heterojunction and a metal-filamentary threshold switch (TS), featuring a vertical transport channel thinner than 5 nm and sub-thermionic turn-on characteristics. The integrated TS-VTFETs were realised with efficient current switching behaviours, exhibiting a current modulation ratio exceeding 1 × 10 8 and an average sub-60 mV/dec SS over 6 decades of drain current. The proposed TS-VTFETs with excellent area- and energy-efficiency could help to tackle the performance degradation-device downscaling dilemma faced by logic transistor technologies.