Optimal Inter-Gate Separation and Overlapped Source of Multi-Channel Line Tunnel FETs
Narasimhulu Thoti, Yiming Li, Sekhar Reddy Kola, Seiji Samukawa
Abstract
This work comprises of design and simulation of multi-channel line tunnel field-effect transistors (mCLTFETs) by scaling inter-gate separation (IGS) and overlapped source (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OV</sub> ). The scope of the work is to explore the performance boost and optimization of the studied devices by considering geometrical structures, low-bandgap materials, IGS and L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OV</sub> of the mCLTFETs. The structure is designed without diminishing the subthreshold swing (SS) and the leakage currents through a spacer technology and strained Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.6</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.4</sub> . The optimal values of IGS and L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OV</sub> for the multi-channel concept are estimated subject to several physical constraints of the proposed device. An IGS ≈ 10 nm and a L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OV</sub> ≈ L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> /2 are reported as suitable choice for sub-8-nm technological nodes, where SS = 18 mV/dec and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> = 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> are achieved.