PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch
P. Schuddinck, F. M. Bufler, Y. Xiang, Anita Farokhnejad, Gioele Mirabelli, A. Vandooren, Bilal Chehab, Anshul Gupta, C. Roda Neve, Geert Hellings, Julien Ryckaert
20222022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)55 citationsDOI
Abstract
We evaluate Power-Performance-Area & Cost (PPAC) for nanosheet (NS), forksheet (FS), monolithic & sequential Complementary FET (CFET) at 5 & 4 track (T) designs with tight gate pitch (CPP) & metal pitch (MP). While NS & FS prove unsuitable for 4T designs, CFETs provide a performant & cost-effective 4T solution.
Topics & Concepts
Track (disk drive)NanosheetComputer scienceElectronic engineeringElectrical engineeringEngineeringMaterials scienceNanotechnologyOperating systemAdvancements in Semiconductor Devices and Circuit DesignSemiconductor materials and devicesFerroelectric and Negative Capacitance Devices