HALO: A Hardware–Software Co-Designed Processor for Brain–Computer Interfaces
Karthik Sriram, Ioannis Karageorgos, Xiayuan Wen, Ján Veselý, Nick Lindsay, Michael Wu, Lenny Khazan, Raghavendra Pradyumna Pothukuchi, Rajit Manohar, Abhishek Bhattacharjee
Abstract
Brain–computer interfaces (BCIs) enable direct communication with the brain, providing valuable information about brain function and enabling novel treatment of brain disorders. Our group has been building Hardware Architecture for Low-power BCIs (HALO), a flexible and ultralow-power processing architecture for BCIs. HALO can process up to 46 Mbps of neural data, a significant increase over the interfacing bandwidth achievable by prior BCIs. HALO can also be programmed to support several applications, unlike most prior BCIs. Key to HALO’s effectiveness is a hardware accelerator cluster, where each accelerator operates within its own clock domain. A configurable interconnect connects the accelerators to create data flow pipelines that realize neural signal processing algorithms. We have taped-out our design in a 12-nm CMOS process. The resulting chip runs at 0.88 V, per-accelerator frequencies of 3–180 MHz, and consumes, at most, 5 mW for each signal processing pipeline. Evaluations using electrophysiological data collected from a nonhuman primate confirm HALO’s flexibility and superior performance per watt.