A 6.5–12-GHz Balanced Variable-Gain Low-Noise Amplifier With Frequency-Selective Gain Equalization Technique
Huiyan Gao, Nayu Li, Min Li, Shaogang Wang, Zijiang Zhang, Yen‐Cheng Kuan, Chunyi Song, Xiaopeng Yu, Qun Jane Gu, Zhiwei Xu
Abstract
This article presents a wideband balanced variable-gain low-noise amplifier (VG-LNA) implemented in a 55-nm CMOS process. The proposed LNA has two cascode stages with an interstage matching transformer to constitute a fourth-order magnetically coupled resonator with two resonant peaks. The frequency-selective gain equalization technique is proposed to compensate for the gain variation of interstage dual-resonant tanks. This VG-LNA leverages a current-steering technique to realize a phase-invariant 18-dB tunable gain range with a measured input 1-dB gain compression point (IP1dB) at 9 GHz from -12.2 to -5 dBm. The LNA achieves a power gain of 20.2 dB with ±0.5-dB gain variation and a noise figure (NF) of 3.26 dB from 6.5 to 12 GHz. Due to the lumped Lange couplers, the input and output matching are both better than -14 dB. This chip occupies 1.44 × 0.68 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area excluding pads and consumes 75 mW.