Design of Multimode In-Memory Computing Architecture Based on SRAM
Youyao Liu, Haihao Wang, Shihao Gai, Qifei Shi
Abstract
With the increasing number of usage scenarios for data-intensive applications, the bottleneck of traditional von-Neumann computing architecture is becoming increasingly apparent, with a large amount of data handling bringing more power consumption and latency. In-memory computing is the embedding of computing units into storage units for data reading and calculation operations, reducing data handling and storage back operations, and reducing power consumption. This article proposes an In-memory computing circuit model based on 9T SRAM, which separates read and write ports to make data more stable. Multiple working modes can also be achieved in SRAM, such as direct calculation of internal and external data in storage units. Finally, simulation was conducted based on the SMIC 0.18um CMOS process. The results indicate that in memory computing with multiple working modes has significant advantages.