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BTI and HCD Degradation in a Complete 32 × 64 bit SRAM Array – including Sense Amplifiers and Write Drivers – under Processor Activity

Victor M. van Santen, Simon Thomann, Chaitanya Pasupuleti, Paul R. Genßler, Narendra Gangwar, Uma Sharma, Jörg Henkel, Souvik Mahapatra, Hussam Amrouch

202022 citationsDOI

Abstract

For the first time, we present a study of BTI and HCD degradation in a 32 × 64 cell SRAM array including Sense Amplifiers (SA), Write Drivers (WD) and pre-charging circuitry (one each for 64 columns) stimulated by the workload-induced activity of a commercial processor. In under 2 hours, our fully automated framework employs the extracted activities to create voltage waveforms used in SPICE simulations (SRAM Array, SA, WD) and degrades transistors using their individual exhibited voltages as stimuli in BTI and HCD models. We support different temperatures, supply voltages (including DVFS), SRAM, SA and WD designs.

Topics & Concepts

Static random-access memorySense amplifierSpiceDegradation (telecommunications)TransistorVoltageAmplifierWaveformSense (electronics)Computer scienceElectrical engineeringElectronic engineeringWorkloadEmbedded systemCMOSEngineeringComputer hardwareOperating systemSemiconductor materials and devicesLow-power high-performance VLSI designAdvancements in Semiconductor Devices and Circuit Design
BTI and HCD Degradation in a Complete 32 × 64 bit SRAM Array – including Sense Amplifiers and Write Drivers – under Processor Activity | Litcius