A Configurable 10T SRAM-Based IMC Accelerator With Scaled-Voltage-Based Pulse Count Modulation for MAC and High-Throughput XAC
Prasanna Kumar Saragada, Subhashish Manna, Amandeep Singh, Bishnu Prasad Das
Abstract
This work proposes a 10T SRAM-based in-memory computation (IMC) architecture that can be configured to perform linear multiply-and-accumulate (MAC) operations and high-throughput XNOR-and-accumulate (XAC) operations. The IMC-MAC operation is performed by using the proposed scaled-voltage-based pulse count modulation (PCM) technique, which improves the linearity and signal margin of the MAC operation. The IMC-XAC operation is performed by using the proposed single capacitor discharge (SCD) approach with various advantages such as no deterministic error in XAC output, low latency, and less variation compared to the traditional charge sharing (TCS)-based XAC operation. The post-layout simulations of the proposed IMC architecture in a 65-nm CMOS process shows that the IMC architecture achieves a signal margin of 44.3 mV using the proposed scaled-voltage-based PCM approach in IMC-MAC mode whereas 37% less variation using the proposed SCD approach in IMC-XAC mode. In IMC-MAC mode, we achieve a 54.6 GOPS, 273 TOPS/W, and 98.67%/88.72% classification accuracy on MNIST/CIFAR-10 dataset using the convolution neural network (CNN)/ResNet20 algorithm. In IMC-XAC mode, we achieve a 3276.8 GOPS, 1092.2 TOPS/W, and 97.12% classification accuracy on the MNIST dataset using the binary neural network (BNN) algorithm.