FPGA Implementation of Deep Neural Network Based Equalizers for High-Speed PON
Noriaki Kaneda, Ziyi Zhu, Chun-Yen Chuang, Amitkumar Mahadevan, Bob Farah, Keren Bergman, Doutje van Veen, Vincent Houtsma
Abstract
A fixed-point deep neural network-based equalizer is implemented in FPGA and is shown to outperform MLSE in receiver sensitivity for 50 Gb/s PON downstream link. Embedded parallelization is proposed and verified to reduce hardware resources.
Topics & Concepts
Field-programmable gate arrayComputer sciencePassive optical networkArtificial neural networkDownstream (manufacturing)Sensitivity (control systems)EqualizerGigabitComputer hardwareReal-time computingElectronic engineeringArtificial intelligenceComputer networkWavelength-division multiplexingTelecommunicationsEngineeringChannel (broadcasting)PhysicsOperations managementOptoelectronicsWavelengthOptical Network TechnologiesAdvanced Photonic Communication SystemsSemiconductor Lasers and Optical Devices