Design of a Low Noise Bio-Potential Recorder With High Tolerance to Power-Line Interference Under 0.8 V Power Supply
Deng Luo, Jiaxin Lei, Milin Zhang, Zhihua Wang
Abstract
A bio-potential recorder working under 0.8 V supply voltage with a tunable low-pass filter is proposed in this paper. The prototype is implemented in TSMC 180 nm CMOS technology, featuring a power consumption of 2.27 μW, while preserving a high tolerance of power-line interference (PLI) up to 600 mV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> , a common-mode rejection ratio (CMRR) of higher than 100 dB, a THD of -65.5 dB, and a noise density of 50 nV/√Hz by employing four new techniques, including 1) low noise chopper modulator, 2) feedback loop based common-mode cancellation loop (CMCL), 3) offset cancellation loop (OCL) with PMOS backgate control scheme, and 4) a very-lower transconductance (VLT) operational transconductance amplifier (OTA) using in the DC-servo-loop (DSL). The measured mid-band gain is 43.3 dB with a high-pass cut-off frequency of 1.2 Hz. The low-pass cut-off frequency can be configured from 650 Hz to 7.5 kHz. The measured input-referred integrated noise is 1.2 uVrms in the frequency band of 1-650 Hz and 4.1 uVrms in the 1 Hz-7.5 kHz frequency band, respectively, leading to a power efficiency factor (PEF) of 7.49 and 7.59.