Package level thermal analysis of backside power delivery network (BS-PDN) configurations
Herman Oprins, Jose L. Bohorquez, Bjorn Vermeersch, Geert Van der Plas, Eric Beyne
Abstract
This paper presents a thermal modeling analysis of the impact of the introduction of a backside power delivery network (BS-PDN) and assesses the trade-off between the beneficial and detrimental thermal consequences of this BS-PDN. In the BS-PDN concept, the power delivery network is moved to the backside of the chip, which enables enhanced system performance, increased chip-area utilization and reduced fine metal pitch BEOL complexity. The connectivity between the backside metals of the PDN and the transistors is provided by means of micro or nano through-Si vias, which requires an extreme thinning of the Si substrate. The potential self-heating issue due to this substrate thinning is the main thermal concern for the backside PDN concept. This paper focuses on the thermal modeling study for a TSV-last BS-PDN concept, for which the TSVs through the Si substrate are processed in the last step, after the processing of the front-end and power rails. A unit cell thermal finite element model of the via-last BS-PDN test case is used with size dependent thermal properties, derived from dedicated nanoscale Monte Carlo simulations. The simulation studies assess the thermal impact of the Si substrate thickness, the backside metals, and the density of the µTSVs.