Design of ternary encoder and decoder using CNTFET
Vikash Prasad, Anirban Banerjee, Debaprasad Das
Abstract
Ternary logic emerges as an alternative to the conventional binary logic in designing high performance, energy-efficient VLSI circuits because it reduces the number of interconnects and chip area. In this paper, we presented low power and high speed 9:2 encoder and 2:9 decoder designs based on ternary logic using carbon nanotube field effect transistors (CNTFETs). These circuits have been extensively simulated at 32 nm CNTFET technology at 0.9 V power supply voltage. The ternary decoder has a power delay product (PDP) of 24.62 aJ and the ternary encoder has a PDP of 133 aJ for a given load. In the proposed designs, the chirality of the carbon nanotube (CNT) is varied to control the threshold voltage. The designs have been analysed with process, voltage and temperature (PVT) variations and it is shown that with PVT variations the performance of the designs vary marginally.