Sub-100 nm Self-Aligned Top-Gate Amorphous InGaZnO Thin-Film Transistors With Gate Insulator of 4 nm Atomic-Layer-Deposited AlO<sub>x</sub>
Yuqing Zhang, Jiye Li, Jinxiong Li, Tengyan Huang, Yuhang Guan, Yuhan Zhang, Huan Yang, Mansun Chan, Xinwei Wang, Lei Lü, Shengdong Zhang
Abstract
We herein demonstrate a self-aligned top-gate (SATG) coplanar amorphous InGaZnO (a-IGZO) thin-film transistor (TFT) technology, with the gate length ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{\text {g}}$ </tex-math></inline-formula> ) down-scaled to 97 nm, and gate insulator (GI) AlOx to 4 nm (equivalent oxide thickness = 2.4 nm). The fabricated TFT exhibits a large on-current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I} _{\text {ON}}$ </tex-math></inline-formula> ) of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$17.9~\mu \text{A}/\mu \text{m}$ </tex-math></inline-formula> , a high on/off current ratio over 109, a positive threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{\text {TH}}$ </tex-math></inline-formula> ) of 0.07 V, and a minimum drain-induced barrier lowering (DIBL) of 77 mV/V. The well-maintained performances of the TFTs even in the nanoscale regime can be ascribed to the abrupt homojunction at source-drain sides and high-quality of ultrathin gate insulator of AlOx by atomic layer deposition (ALD). With the excellent scaling metrics and compatibility with modern integrated circuit (IC) process, the developed SATG a-IGZO TFT technology is compatible with the back-end-of-line(BEOL) and 3D integrations of advanced ICs.