Litcius/Paper detail

Die to Wafer Hybrid Bonding and Fine Pitch Considerations

Thomas Workman, Laura Mirkarimi, Jeremy Theil, G. G. Fountain, KM Bang, Bongsub Lee, Cyprian Uzoh, Dominik Suwito, Guilian Gao, P. Mrozek

202130 citationsDOI

Abstract

Hybrid bonding is becoming increasingly important as the semiconductor industry plans for the next generation of packaging where high bandwidth architectures are required to achieve improved compute performance demands. The scalability challenges in solder-based interconnects at <; 35 μm pitch has fueled the adoption of hybrid bonding as a technology with enhanced scalability. The direct bond interconnect (DBI®) technology which was developed originally for wafer to wafer (W2W) applications has been extended to die to wafer (D2W) as DBI® Ultra. In this paper, we discuss the test results for a new die to wafer hybrid bonding test vehicle with an interconnect design of 2 μm pad on 4 μm pitch. The 8 mm by 12 mm chip contains daisy chain test structures ranging from 126,000 to 1,600,000 links. The component die wafers were singulated with conventional stealth dicing and then processed on tape frame for preparation of D2W bonding. The 2 μm bond pad requires sub-micron alignment accuracy within the pick and place tool for 100% alignment yield. However, due to bonder availability, our initial trials were bonded on a Besi Chameo Advanced bonder with an ISO 3 bonding environment and an alignment accuracy of +/- 3 μm (3 σ). The bond quality is characterized with C-mode scanning acoustic microscopy (CSAM), electrical resistance measurement, and cross-section microscopy analysis. The bond yield is shared as a function of bond defect density and electrical yield. Daisy chain yield and resistance versus misalignment for the fine pitch test vehicle are compared to test vehicles having a 10 μm pad on 40 μm pitch. The implications of the 10x pitch shrink on process control from wafer and die fabrication are discussed.

Topics & Concepts

Daisy chainWaferWafer dicingWafer bondingInterconnectionWafer testingDie (integrated circuit)Materials scienceWire bondingLead frameElectronic engineeringIntegrated circuit packagingChip-scale packageOptoelectronicsChipComposite materialComputer scienceNanotechnologySemiconductor deviceElectrical engineeringIntegrated circuitEngineeringComputer hardwareLayer (electronics)Telecommunications3D IC and TSV technologiesElectronic Packaging and Soldering TechnologiesVLSI and FPGA Design Techniques