Integrating Chiplets using Chips First Ultra-High-Density Fan-out with Maskless Laser Direct Imaging and Adaptive Patterning for High Performance Computing

Abstract

Our industry has entered the chiplet era where scaling and performance improvements are enabled through the heterogenous integration of various functions and wafer fab technology nodes through advanced packaging technology. Deca's M-Series™ is a chips-first, face-up FOWLP (fan-out wafer level packaging) technology which includes a highly planar surface for RDL build-up where the semiconductor device active surface and vertical sidewalls are fully encapsulated with an epoxy molding compound (EMC) or other dielectric material. Through scaling to 2µm lines & spaces and multiple redistribution layers (RDL), the M-Series provides powerful new possibilities for chiplet-based architectures moving to higher bandwidth interfaces where designers favor multiple parallel interconnects over classic SERDES connections. The desire for thousands of chiplet-to-chiplet connections is driving an unprecedented need for shrinking the device bond pad pitch especially for applications such as high-performance computing. A major barrier in shrinking the device bond pad pitch is die shift. Die shift is the natural variation in die location within an embedded structure stemming from chip attach, molding, and other process variables. Chips-first fan-out technologies using conventional design methods and mask-based lithography run into barriers in the range of 45µm device bond pad pitch due to the need for large capture pads which account for typical die shift. The M-Series overcomes die shift using Adaptive Patterning® (AP) with its unique design-during-manufacturing methods and mask-less laser direct imaging (LDI) photolithography. AP enables a precise RDL via connection to each device bond pad or additional layer by precisely aligning a unit-specific pattern to every device. The second-generation M-Series with Adaptive Patterning, or Gen 2, opens up an unprecedented 20µm area array pitch bond pads as a starting point with a roadmap to achieve 10µm bond pad pitch in the near future. In this paper, we will discuss preliminary Gen 2 design rules and their implementation on a test vehicle jointly produced by Deca and nepes hayyim. The test vehicle has two Chips First chiplet processors and four simulated footprints for high bandwidth memory (HBM) modules which would be mounted Chips Last. In order to enable ultra-high-density interconnect on Gen 2, the design rules allow for a 20µm device bond pad pitch and 2µm lines & spaces. The design and construction of the Gen 2 test vehicle will be examined.

Topics & Concepts