Device Design Guidelines of 3-nm Node Complementary FET (CFET) in Perspective of Electrothermal Characteristics
Seung-Geun Jung, Dong-Won Jang, Seong-Ji Min, Euyjin Park, Hyun‐Yong Yu
Abstract
For the first time, device design guidelines for a 3-nm node complementary field-effect transistor (CFET), which vertically stacks n-type and p-type nanosheet MOSFETs with a shared gate, are investigated using calibrated 3-D technology computer-aided design (TCAD). Here, the optimal device dimensions of the CFETs for better inverter performance and thermal characteristics are studied. The electrothermal performance are investigated for various vertical dimension parameters of CFET, such as the number of stacked channels, vertical distance between nanosheet channels (D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nsh</sub> ), distance of n/pMOS separation (D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n/p</sub> ), and channel thicknesses (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nsh</sub> ). The results show that, unlike conventional CMOS, the reduction of D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nsh</sub> and D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n/p</sub> of CFET can effectively improve inverter performance without severe thermal degradation, although other dimensional parameters trigger a severe trade-off between different electrothermal parameters. The reduction of D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nsh</sub> and D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n/p</sub> decreases C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> with a lower metal via the height and gate fringing effect. However, the reduction in D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nsh</sub> and D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n/p</sub> does not change R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> ; therefore, both the operation frequency ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f$ </tex-math></inline-formula> ) and power-product delay (PDP) can be improved. In the case of thermal characteristics, the reduction of D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nsh</sub> and D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n/p</sub> slightly increases both T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> and R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> because of thermal coupling but is negligible. Therefore, the reduction of D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nsh</sub> and D <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n/p</sub> will be a key technique for the development of sub-3-nm CFET.