Novel FDSOI-based Dynamic XNOR Logic for Ultra-Dense Highly-Efficient Computing
Shubham Kumar, Swetaki Chatterjee, Chetan Kumar Dabhi, Hussam Amrouch, Yogesh Singh Chauhan
Abstract
For the first time, we propose a novel circuit for dynamic 2-input XNOR gate that merely employs two n-type Fully-Depleted Silicon on Insulator (nFDSOI) FETs along with one additional precharging pFDSOI FET. Our design exploits the threshold voltage (V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</inf> ) tuning feature (i.e., 1ow-V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</inf> and high-V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</inf> states) of FDSOI FET using the back bias as one input. The front gate bias is used as a second input. The proposed novel XNOR design reduces the number of transistors and significantly reduces power, delay, and energy compared to state-of-the-art dynamic XNOR gates. To accurately evaluate the Figure of merits, the industrial transistor compact model has been carefully calibrated against industrial measurements. The analysis demonstrates that our novel XNOR gates exhibits $8\times$ improvement in the propagation delay and $17\times$ improvement in the power consumption compared to the state-of-the-art dynamic XNOR design. Additionally, we explore the critical role of the buried oxide (BOX) thickness on the performance of proposed XNOR design.