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Highly Independent MTJ-Based PUF System Using Diode-Connected Transistor and Two-Step Postprocessing for Improved Response Stability

Sehee Lim, Byungkyu Song, Seong‐Ook Jung

2020IEEE Transactions on Information Forensics and Security28 citationsDOI

Abstract

In physically unclonable functions (PUFs), generating random cryptographs is required to secure private information. Various memory-based PUFs (MemPUFs), where cryptographs are generated independently from each PUF cell to increase the unpredictability of the cryptographs, have been proposed. Among them, the spin-transfer torque magnetic random-access memory MemPUF generates constant responses under temperature and voltage variations by exploiting a magnetic tunnel junction (MTJ) as the variation source. However, its response stability is diminished by the different characteristics of the two access transistors used in a PUF cell. To solve this problem, a novel PUF array that employs a diode-connected transistor and a shared access transistor, is proposed. In addition, a two-step postprocessing is adopted: 1) a write-back technique that amplifies the initial mismatch of MTJ resistances, and 2) a cell-classification technique that detects unstable PUF cells and discards their responses. The Monte Carlo HSPICE simulation results using industry-compatible 65-nm technology show that the proposed PUF system achieves the highest independence (autocorrelation factor of 0.0306) and the lowest maximum bit error rate (BER) under temperature and supply-voltage variations (<; 0.01% and 0.04% in the ranges of -25 to 75 °C and 0.8-1.2 V, respectively) compared with conventional PUF systems that exploit independent variation sources.

Topics & Concepts

TransistorComputer sciencePhysical unclonable functionSpin-transfer torqueVoltageElectronic engineeringMaterials scienceElectrical engineeringComputer hardwareEngineeringPhysicsArbiterQuantum mechanicsMagnetic fieldMagnetizationPhysical Unclonable Functions (PUFs) and Hardware SecurityAdvanced Memory and Neural ComputingIntegrated Circuits and Semiconductor Failure Analysis