Integration of 0.75 V V<sub>DD</sub> Oxide-Semiconductor 1T1C Memory with Advanced Logic for an Ultra-Low-Power Low-Latency Cache Solution
Katherine Chiang, Yen-Chung Ho, Ming-Yen Chuang, Chih‐Yu Chang, Yun-Feng Kao, Hsin‐Yi Yang, C.‐M. Huang, Yu-Jen Chien, Yin-Hao Wu, Yi-Ching Liu, Hiroki Noguchi, Chengjun Wu, Wai-Kit Lee, Chen-Han Chou, Pei-Jean Liao, Yu‐Chien Chiu, Ya-Yun Cheng, Yu-Ming Lin, Yih Wang, Jonathan Chang, Chung-Te Lin, Min Cao
Abstract
We successfully demonstrated the monolithic integration of a BEOL memory with advanced logic. The memory array is completely embedded in the BEOL, featuring an oxidesemiconductor channel selector and a low-temperature process capacitor. Yield and reliability were verified on a memory test chip operating at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.75 \mathrm{V} \mathrm{V}_{\text{DD}}$</tex>, with active energy lower than <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.5 \text{pJ} / \mathrm{b}$</tex> and a random cycle time of less than 8 ns, achieving retention exceeding 128 ms and endurance surpassing 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">14</sup> cycles at 85° C. This advanced logic-compatible BEOL memory technology offers a customizable, ultra-low-power, low-latency cache solution with a higher density than SRAM.