Van der Waals polarity-engineered 3D integration of 2D complementary logic
Yimeng Guo, Jiangxu Li, Xuepeng Zhan, Chunwen Wang, Min Li, Biao Zhang, Zirui Wang, Yue‐Yang Liu, Kaining Yang, Hai Wang, Wanying Li, Pingfan Gu, Zhaoping Luo, Yingjia Liu, Peitao Liu, Bo Chen, Kenji Watanabe, Takashi Taniguchi, Xing‐Qiu Chen, Chengbing Qin, Jiezhi Chen, Dongming Sun, Jing Zhang, Runsheng Wang, Jianpeng Liu, Yu Ye, Xiuyan Li, Yanglong Hou, Wu Zhou, Hanwen Wang, Zheng Han, Hanwen Wang, Zheng Han
Abstract
Abstract Vertical three-dimensional integration of two-dimensional (2D) semiconductors holds great promise, as it offers the possibility to scale up logic layers in the z axis 1–3 . Indeed, vertical complementary field-effect transistors (CFETs) built with such mixed-dimensional heterostructures 4,5 , as well as hetero-2D layers with different carrier types 6–8 , have been demonstrated recently. However, so far, the lack of a controllable doping scheme (especially p-doped WSe 2 (refs. 9–17 ) and MoS 2 (refs. 11,18–28 )) in 2D semiconductors, preferably in a stable and non-destructive manner, has greatly impeded the bottom-up scaling of complementary logic circuitries. Here we show that, by bringing transition metal dichalcogenides, such as MoS 2 , atop a van der Waals (vdW) antiferromagnetic insulator chromium oxychloride (CrOCl), the carrier polarity in MoS 2 can be readily reconfigured from n- to p-type via strong vdW interfacial coupling. The consequential band alignment yields transistors with room-temperature hole mobilities up to approximately 425 cm 2 V −1 s −1 , on/off ratios reaching 10 6 and air-stable performance for over one year. Based on this approach, vertically constructed complementary logic, including inverters with 6 vdW layers, NANDs with 14 vdW layers and SRAMs with 14 vdW layers, are further demonstrated. Our findings of polarity-engineered p- and n-type 2D semiconductor channels with and without vdW intercalation are robust and universal to various materials and thus may throw light on future three-dimensional vertically integrated circuits based on 2D logic gates.