Low-Density Parity-Check Coded Direct Sequence Spread Spectrum Receiver Based on Analog Probabilistic Processing
Xuhui Ding, Jianping An, Zhe Zhao, Xiangyuan Bu, Kai Yang
Abstract
Forward error correction (FEC) coding is an indispensable technique in the direct sequence spread spectrum (DS-SS) systems for satellite communication applications. Both the FEC and DS-SS can be regarded as specific cases of probabilistic computing based on analog circuits, which is expected to be a promising solution for power-limited scenarios. The combination of FEC and DS-SS techniques can provide sufficient link margin and robustness for communication systems. In this paper, a probabilistic receiver chain for the Low-Density Parity-Check (LDPC) coded DS-SS system is proposed. Generically, an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$m$</tex-math></inline-formula> -sequence can be regarded as a codeword of cyclic linear codes. Similar to the decoding procedure of LDPC codes, the joint detection and decoding process of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$m$</tex-math></inline-formula> -sequences can be performed by factor graph-based iterative message-passing algorithms (iMPAs). In terms of the iterative signal processing, we first present an improved approach of iterative stopping criterion which can reduce the average number of iteration by 90% for the LDPC decoding approach. Furthermore, a joint detection and decoding method is developed to provide quick synchronization of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$m$</tex-math></inline-formula> -sequence. Meanwhile, stopping criterion-based iMPAs are especially suitable for analog implementation with low complexity. Finally, cascading to the analog LDPC decoder, the implementation of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$m$</tex-math></inline-formula> -sequence detector is designed. The prototyping chip is fully integrated into a 0.35- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\mu\text{m}$</tex-math></inline-formula> CMOS technology, which can achieve higher throughput than 3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">${\textbf {Gcps}}$</tex-math></inline-formula> with a core chip area of 2.79 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">${\textbf {mm}}^2$</tex-math></inline-formula> and power consumption of 6.99 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">${\textbf {mW}}$</tex-math></inline-formula> for its core circuit. Experimental results demonstrate the effectiveness of our proposed receiver mechanism.