Deep Neural Network (DNN) Optimized Design of 2.45 GHz CMOS Rectifier With 73.6% Peak Efficiency for RF Energy Harvesting
Wendy Wee Yee Lau, Heng Wah Ho, Liter Siek
Abstract
This article presents a two-stage rectifier with novel DC-boosted gate bias for RF energy harvesting. The auxiliary gate bias enables rectifier to operate when input amplitude is smaller than its transistor threshold voltage while constraining the positive gate voltage during off state to reduce the reverse leakage current. An automated design optimization methodology using Deep Neural Network (DNN) to maximize efficiency is presented. The DNN is shown to accurately model SPICE simulated response of rectifier. Hence, the design phase turnaround time is minimized with fast prediction of optimized design parameters. The proposed rectifier has been fabricated in 65 nm standard CMOS technology. A maximum power conversion efficiency of 73.6% is measured at 2.45 GHz with input power of -6 dBm. The proposed rectifier has a measured sensitivity of -12 dBm for 1 V output voltage.