A Review of the Gate-All-Around Nanosheet FET Process Opportunities
Sagarika Mukesh, Jingyun Zhang
Abstract
In this paper, the innovations in device design of the gate-all-around (GAA) nanosheet FET are reviewed. These innovations span enablement of multiple threshold voltages and bottom dielectric isolation in addition to impact of channel geometry on the overall device performance. Current scaling challenges for GAA nanosheet FETs are reviewed and discussed. Finally, an analysis of future innovations required to continue scaling nanosheet FETs and future technologies is discussed.
Topics & Concepts
NanosheetScalingNanotechnologyMaterials scienceDielectricChannel (broadcasting)Electronic engineeringProcess (computing)OptoelectronicsEngineering physicsEngineeringElectrical engineeringComputer scienceOperating systemMathematicsGeometrySemiconductor materials and devicesAdvancements in Semiconductor Devices and Circuit DesignFerroelectric and Negative Capacitance Devices