FliT
Yuanhao Wei, Naama Ben-David, Michal Friedman, Guy E. Blelloch, Erez Petrank
Abstract
Non-volatile random access memory (NVRAM) offers byte-addressable persistence at speeds comparable to DRAM. However, with caches remaining volatile, automatic cache evictions can reorder updates to memory, potentially leaving persistent memory in an inconsistent state upon a system crash. Flush and fence instructions can be used to force ordering among updates, but are expensive. This has motivated significant work studying how to write correct and efficient persistent programs for NVRAM.
Topics & Concepts
Non-volatile random-access memoryComputer scienceDramCacheCrashParallel computingOperating systemNon-volatile memoryRandom access memoryByteEmbedded systemSemiconductor memoryComputer hardwareMemory refreshComputer memoryParallel Computing and Optimization TechniquesAdvanced Memory and Neural ComputingDistributed systems and fault tolerance