Adaptive And Recursive Vedic Karatsuba Multiplier Using Non Linear Carry Select Adder
M. Saritha, Kancharapu Chaitanya, Vallabhuni Vijay, Adam Aishwarya, Hasmitha Yadav, G. Durga Prasad, K Jaiswal, Nithish Kumar, V, P Seshadri, G Lakshminarayanan, Rajeev Vallabhuni, Jujavarapu Sravana, Chandra Shaker Pittala, Mikkili Divya, B Rani, Vallabhuni Vijcaay, Vallabhuni Vijay, Pittala Chandra Shekar, Shaik Sadulla, Putta Manoja, Rallabhandy Abhinaya, Nakka Merugu, Nikhil, Vallabhuni, C Vijay, Chandrashaker Sai Kumar Reddy, Pittala, B Rani, Ch, Srivalli, Rajeev Ratna Vallabhuni, S Lakshmanachari, G Avanthi, Vallabhuni Vijay, Chandra Shaker Pittala, Chandra Shaker Pittala, M Vallabhuni Rajeev Ratna, Saritha, V Saipreethi, P Vijay, Chandra, M Shaker, Shaik Divya, Sadulla, Manchala Sreeja, Vallabhuni Vijay, S Kakde, S Khan, P Dakhole, S Badwaik, V Vijay, Ch, Srivalli, Chandra Shaker, Pittala, Vallabhuni Vijay, Vallabhuni, Vijay, S Swathi, S Prasad, Chandra Shaker Pittala, V Vijay, Rajeev Vallabhuni, Bandi Mary, Sowbhagya Rani, Devi Vasumathi, Chandra Majety, Vallabhuni Shaker Pittala, Kanumalli Vijay, Siripuri Satya Sandeep, Kiran, K Bindu, Chandra Shaker Pittala, S Pohokar, R Sisal, K Gaikwad, M Patil, R Borse, S Arish, R Sharma, Vallabhuni, C Vijay, Chandrashaker Sai Kumar Reddy, P Ashok Pittala, Babu, Vallabhuni, C Vijay, Veerastu Sai Kumar Reddy, Chandrashaker Sivanagaraju, Pittala, Vallabhuni, C Vijay, Chandrashaker Sai Kumar Reddy, Pittala, China Sonagiri, Venkateswarlu, Rajeev Ratna Vallabhuni, M Saritha, Sruthi Chikkapally
Abstract
Multipliers play a vital role in any applications like signal processing, image processing, floating-point processors etc. These applications require efficient binary multiplications, but it is most powerful as well as time consuming process. An efficient binary multiplication is proposed to reduce the delay. Vedic Karatsuba multiplier is an efficient algorithm which can be used to reduce the delay. The combination of adaptive and recursive approach of Vedic Karatsuba algorithm along with Non - Linear Carry Select Adder is implemented to get the better results. Multiplier designs are coded in Verilog by using Xilinx software