Restructure-Tolerant Timing Prediction via Multimodal Fusion

Ziyi Wang, Siting Liu, Yuan Pu, Song Chen, Tsung-Yi Ho, Bei Yu

202331 citationsDOI

Abstract

Fast and accurate pre-routing timing prediction is crucial in the very-large-scale integration (VLSI) design flow. Existing machine learning (ML)-assisted pre-routing timing evaluators neglect the impact of timing optimization, which may render their approaches impractical in real circuit design flows. To model the impact of timing optimization, we propose an endpoint embedding framework that integrates netlist-layout information via multimodal fusion. An end-to-end flow is further developed for pre-routing restructure-tolerant prediction on global timing metrics. Comprehensive experiments on large-scale RISC-V designs with advanced 7-nm technology node demonstrate the superiority of our model compared to the SOTA pre-routing timing evaluators.

Topics & Concepts

Computer scienceNetlistStatic timing analysisRouting (electronic design automation)Very-large-scale integrationComputer architectureDistributed computingParallel computingEmbedded systemVLSI and Analog Circuit TestingVLSI and FPGA Design TechniquesIntegrated Circuits and Semiconductor Failure Analysis