Highly Efficient Differential Frequency Doubler With Output Resistance Boosting Feedback
Jong‐Ho Yoo, Songcheol Hong
Abstract
This article presents a differential <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V$ </tex-math></inline-formula> -band frequency doubler and a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$D$ </tex-math></inline-formula> -band frequency quadrupler that use complementary MOS transistors. The frequency doubler is designed to achieve high conversion efficiency (CE) by utilizing the feedback effect due to the gate–drain parasitic capacitance and the series inductor at the gate of the transistors. Capacitors are added to NMOS transistors to alleviate the intrinsic imbalances between NMOS and PMOS transistors. The frequency quadrupler is composed of cascaded differential doublers. Both frequency multipliers are fabricated in a 40 nm bulk CMOS process. The proposed frequency doubler demonstrates a CE rate of 15.3%, an output power of 3.5 dBm, and a conversion gain (CG) of 0.0 dB. The proposed frequency quadrupler demonstrates a CE rate of 4.7%, an output power of 1.3 dBm, and a CG of −1.0 dB. The CEs of both differential frequency multipliers are the highest among reported CMOS multipliers for their respective frequency bands.