Functional Interposer Embedded with Multi-Terminal Si Capacitor for 2.5D/3D Applications Using Planarization and Bumpless Chip-on-Wafer (COW)
Yoshiaki Satake, Tatsuya FUNAKI, Kyosuke Kobinata, Hitoshi Matsuno, Seiji Hidaka, Shunsuke Abe, Hiroyuki Ito, Chih-Cheng Hsiao, Sheng Yi Li, Young-Suk Kim, Takayuki Ohba
Abstract
A multi-terminal Si capacitor with low equivalent series inductance (ESL) for power delivery systems in 2.5D/3D applications was demonstrated. The shortest parallel interconnects with a length of 20 μm from a power delivery network of RDL to the capacitor were successfully fabricated, in a 3D functional interposer, a Si capacitor is connected through Cu pads and through silicon vias (TSVs) formed by a bumpless Chip-on-Wafer (COW) process. By optimizing the capacitor direct-stack process with an adhesive curing profile and a TSV profile hy dry etching, 700 TSV connections with no open failures were achieved.