A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge Applications

Chia-Fu Lee, C.W. Lu, Cheng-En Lee, H. Mori, Hidehiro Fujiwara, Yi-Chun Shih, Tan‐Li Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang

20222022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)77 citationsDOI

Abstract

Recently SRAM-based digital compute-in memory (D-CIM) [1] has demonstrated excellent energy/area efficiency, with full precision of 4b/8b integer multiply-accumulate operations, it has better programmability, hardware reuse and scalability, in addition, it can effectively leverage technology scaling for better PPA. Nonetheless, several new challenges remain, including huge peak currents resulting from high parallel operation, long delays in adder trees, and scalable architectures that support various neural network topologies. In this paper, we detail proposed solutions to address the new challenges and present measurement results for a SRAM-based 64x64 CIM manufactured by 12nm CMOS process.

Topics & Concepts

Static random-access memoryScalabilityComputer scienceAdderLeverage (statistics)Parallel computingTOPSEnhanced Data Rates for GSM EvolutionComputer hardwareField-programmable gate arrayScalingNetwork topologyCMOSComputer architectureElectronic engineeringEngineeringArtificial intelligenceDatabaseSpinningMechanical engineeringMathematicsGeometryOperating systemAdvanced Memory and Neural ComputingFerroelectric and Negative Capacitance DevicesParallel Computing and Optimization Techniques