11.1 A Scalable Heterogeneous Integrated Two-Stage Vertical Power-Delivery Architecture for High-Performance Computing

Abstract

Emerging high-performance computing needs in data center, autonomous vehicle, and mobile device processors demand increasingly large peak currents at scaled-CMOS-compatible voltages (<1V). To ease otherwise high <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{I}^{2}\mathrm{R}$</tex> losses in power delivery (PD), most applications now target high system-level voltage busses (e.g., 20V) prior to arriving at the processor load. However, voltage incompatibility with scaled CMOS means that conventional approaches require a voltage regulator module (VRM) located laterally off-chip [1] for conversion down to a lower rail (e.g., 1.8V), followed by a fully integrated voltage regulator (FIVR) using external LC filters with inductors embedded into the package substrate [2] (Fig. 11.1.1). The large conversion ratio required by the VRM and the large lateral interconnect losses from the VRM to the processor, followed by low-voltage/high-currents (LV/HC) that flow out of the FIVR to the substrate conductors/passives and then back into the processor at even lower voltages/higher currents, limit the overall efficiency to ~80 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">%</sup> , which is not sufficient to meet the needs of emerging energy and thermally-constrained systems. Additionally, LV/HC processor PD requires a large number of pins (e.g.,~50 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">%</sup> of all pins for power/gnd), which is problematic for emerging AI/ML applications that require pin-intensive high-throughput memory access. These issues are exacerbated in future systems where more heterogeneous integration (HI) is required.

Topics & Concepts