High Performance (V<sub>th</sub> ~ 0 V, SS ~ 69 mV/dec, I<sub>On</sub>/I<sub>Off</sub> ~ 10<sup>10</sup>) Thin-Film Transistors Using Ultrathin Indium Oxide Channel and SiO<sub>2</sub> Passivation
Dongqi Xiao, Binbin Luo, Chun-Ming Huang, Wenjie Xiong, Xiaohan Wu, Shi‐Jin Ding
Abstract
Ultrathin indium oxide (InO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><i>x</i></sub> ) films (≤5 nm), which are grown by plasma-enhanced (PE) atomic layer deposition (ALD) with (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sub> ) <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> InCH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> and O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> plasma, are explored as channels of thin-film transistors (TFTs). First, we investigate the effects of channel thickness ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${T}_{\text{ch}}$ </tex-math></inline-formula> ), channel length ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}_{\text{ch}}$ </tex-math></inline-formula> ), and post-annealing conditions on the performance of TFTs with HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate dielectrics, respectively. The results indicate that superior overall performance can be achieved for the device with 2.5 nm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${T}_{\text{ch}}$ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2 ~\mu \text{m} {L}_{\text{ch}}$ </tex-math></inline-formula> , and 8.5 nm HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate dielectric after annealing at 325 °C for 180 s in O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> . Increasing the post-annealing temperature to 350 °C degrades the TFTs because of crystallization of HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and outdiffusion of In element. Furthermore, with a PE chemical vapor-deposited SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> passivation layer on the back of the channel, the performance of the TFTs is significantly improved after post-annealing, especially at 300 °C for 1 h in air, such as near-zero-threshold voltage, a very small subthreshold slope (SS) of 69 mV/dec, a very high On/Off current ratio of ~10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> , and relatively high field effect mobility of 17 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> / <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}\cdot \text{s}$ </tex-math></inline-formula> . Finally, the positive and negative gate bias stress (NGBS) measurements of the devices also indicate that the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> passivation layer can improve remarkably the NGBS stability. Thus, such a kind of device could be very promising for low-voltage and low-power applications.