Improved MW of IGZO-channel FeFET by Reading Scheme Optimization and Interfacial Engineering
Zhuo Chen, N. Ronchi, A. Walke, Kaustuv Banerjee, M. Popovici, Kostantine Katcko, G. Van den bosch, M. Rosmeulen, Valeri Afanas’ev, Jan Van Houdt
Abstract
We fabricated and characterized IGZO-channel back-gated FeFET. It has been found that a Memory Window (MW) reading scheme based on reverse $I_{d}-V_{g}$ sweep can strongly attenuate the significant read disturb which affects the low- V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</inf> state. This instability of low- $\mathrm{V}_{\mathrm{t}}$ state origins from the asymmetric PV loop and small negative coercive voltage. With this optimized reading scheme, we proved that interfacial engineering, by inserting a $\mathrm{NbO}_{\mathrm{x}}$ layer between La HZO and IGZO, can significantly improve $2 P_{r}$, MW (to $0.7 \mathrm{~V}$), and endurance (to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> cycles). This makes the $\mathrm{La}: \mathrm{HZO} / \mathrm{NbO}_{\mathrm{x}} / \mathrm{IGZO}$ FeFET a promising structure for high-endurance and low-latency NVM.