Litcius/Paper detail

A 112.5Gb/s ADC-DSP-Based PAM-4 Long-Reach Transceiver with >50dB Channel Loss in 5nm FinFET

Z. Guo, A. Mostafa, A. Elshazly, Bo-Yi Chen, B. Wang, Changzhong Han, C. Wang, D. Zhou, D. Visani, E. Hsiao, F. Chu, F. Lu, Guangxu Cui, Hai Zhang, H. Wang, Hui Zhao, J. Lin, J. Gu, L. Luo, L. Jiang, M. Singh, Manisha Gambhir, M. Hasan, M. Wu, Mina Yoo, P. Liu, S. Kollu, Tone Ye, Xinye Zhao, Xiaochen Yang, X. Han, Yuexun Huang, Yehui Sun, Z. Yu, Z. H. Jiang, Z. Adal, Zaolin Yan

20222022 IEEE International Solid- State Circuits Conference (ISSCC)54 citationsDOI

Abstract

With increasing demand in next-generation data centers and high-performance computing and networking, wireline transceivers are required to operate at 112Gb/s to provide high bandwidth [1]–[3], meanwhile it is necessary to handle >40dB insertion loss to support legacy channels and large package designs [4]. Low-power design is also critical for the integration of multiple transceivers [5]. To advance state-of-the-art design, this work presents an ADC/DAC-DSP based PAM-4 transceiver capable of equalizing >50dB lossy channels and achieving 112.5Gb/s per channel in a 5nm FinFET process with a power efficiency of 4.5pJ/b.

Topics & Concepts

TransceiverWirelineElectronic engineeringDigital signal processingSerDesBandwidth (computing)Computer scienceChannel (broadcasting)EngineeringElectrical engineeringComputer hardwareWirelessTelecommunicationsCMOSSemiconductor materials and devicesVLSI and Analog Circuit TestingAdvancements in PLL and VCO Technologies
A 112.5Gb/s ADC-DSP-Based PAM-4 Long-Reach Transceiver with >50dB Channel Loss in 5nm FinFET | Litcius