A 25.8GHz Integer-N PLL With Time-Amplifying Phase-Frequency Detector Achieving 60fs<sub>rms</sub> Jitter, -252.8dB FoM<sub>J</sub>, and Robust Lock Acquisition Performance
Xinlin Geng, Yibo Tian, Yao Xiao, Zonglin Ye, Qian Xie, Zheng Wang
Abstract
With the rapid development of the modern communication technology, the communication standards impose stringent performance requirements, such as the ultra-low jitter requirement, on the phase-locked-loop (PLL) frequency synthesizers. As one of the widest-employed PLL structures, a charge-pump PLL (CPPLL) with a phase-frequency detector (PFD) is known for its excellent robust lock-acquisition performance due to the capability to detect phase and frequency error simultaneously. Recent research exhibited the great potential of the CPPLLs to achieve sub-100fs <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</inf> jitter [1]. However, a large current CP is adopted in [1] to minimize CP noise at the cost of high-power consumption. In this work, a 25.8GHz PLL with a time-amplifying phase-frequency detector (TAPFD) is implemented to suppress the CP noise by the high phase-error detection gain of the TAPFD and maintain the robust acquisition ability concurrently. The prototype is measured to achieve 60fs <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</inf> jitter and -252.8dB FoM <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">J</inf> .