Accelerating RTL Simulation with Hardware-Software Co-Design
Fares Elsabbagh, Shabnam Sheikhha, Victor A. Ying, Q. Nguyen, Joel Emer, Daniel Sánchez
Abstract
Fast simulation of digital circuits is crucial to build modern chips. But RTL (Register-Transfer-Level) simulators are slow, as they cannot exploit multicores well. Slow simulation lengthens chip design time and makes bugs more frequent.
Topics & Concepts
Computer scienceExploitRegister-transfer levelEmbedded systemLogic simulationComputer architectureSystem on a chipSoftwareChipDigital electronicsElectronic design automationIntegrated circuit designComputer hardwareLogic synthesisElectronic circuitLogic gateOperating systemEngineeringComputer securityAlgorithmElectrical engineeringTelecommunicationsParallel Computing and Optimization TechniquesSimulation Techniques and ApplicationsEmbedded Systems Design Techniques