Effects of NBTI On PMOS Device With Technology Scaling

S M Shakil, Muhammad Sana Ullah

20222022 IEEE 13th Annual Ubiquitous Computing, Electronics & Mobile Communication Conference (UEMCON)16 citationsDOI

Abstract

Negative bias temperature instability (NBTI) is caused by a physical mechanism that increased the fault sensitivity of metal oxide semiconductor field-effect transistors (MOSFETs) which jeopardizes the device’s normal functioning. This article discusses the effect of physical miniaturization on MOSFET reliability at various technology nodes and observe threshold voltage changes with respect to different process and parameters for PMOS transistors. In addition, it is discussed a predictive model that recently developed for NBTI concepts using the traditional reaction-diffusion (R-D) model. Based on this RD model, it is analyzed the threshold voltage with scaling effects for 65nm, 45nm, and 32nm technology nodes. Besides, different ways to reduce the NBTI issues are discussed. It is suggested that NBTI could be optimized by using the amorphous plasma nitride instead of oxide nitride, tuned the power supply and threshold voltage, and lowered the duty cycle.

Topics & Concepts

PMOS logicScalingMaterials scienceNegative-bias temperature instabilityNMOS logicLogic gateOptoelectronicsMOSFETEngineering physicsElectrical engineeringTransistorVoltageEngineeringGeometryMathematicsSemiconductor materials and devicesAdvancements in Semiconductor Devices and Circuit DesignIntegrated Circuits and Semiconductor Failure Analysis