A 0.5µm Pixel 3-layer Stacked CMOS Image Sensor with Deep Contact and In-pixel Cu-Cu Bonding Technology
Gwi-Deok Ryan Lee, Dae‐Hoon Kim, Doowon Kwon, Jong‐Eun Park, Dongseok Cho, Jeongsoon Kang, Gyunha Park, Junha Kang, Min‐Ho Jang, Seungjae Oh, Doyeon Kim, Sol Yoon, Yongjun Kim, Sejin Park, Kyungtae Lim, Dong-Jun Oh, Soo-Young Kang, Keunhyoung Park, Changhwa Kim, Hyo Ju Kim, Taeyeong Kim, K H Lee, H. Cho, Son-Kwan Hwang, Hojin Lee, Jae-Kyu Lee, Hyunchul Kim, Chang-Rok Moon, Jaihyuk Song
Abstract
64Mp CIS with 0.5um pixels has been developed with three wafer layers (e.g. top-wafer for PDs and TG TRs, mid-wafer for pixel TRs, and bottom-wafer for the analog and logic circuits). The RTS noise was reduced by 85% compared to ones of the conventional structure with over 6,000e-FWC as similar to our previous research [1] - [3]. In addition, the FD conversion gain was improved by 67% with the Miller effect due to the reduction of the DCNT capacitance.