Heterogeneous 3-D Sequential CFETs With Ge (110) Nanosheet p-FETs on Si (100) Bulk n-FETs
Seong Kwang Kim, Hyeong-Rak Lim, Jaejoong Jeong, Seung Woo Lee, Ho Jin Jeong, Juhyuk Park, Joon Pyo Kim, Jaeyong Jeong, Bong Ho Kim, Seung-Yeop Ahn, Youngkeun Park, Dae-Myoung Geum, Younghyun Kim, Yongku Baek, Byung Jin Cho, Sanghyeon Kim
Abstract
In this study, we report on the fabrication and characterization of 3-D sequential complementary field-effect-transistors (CFETs) using the direct wafer bonding (DWB) technology and a low-temperature process for monolithic 3-D (M3D) integration. The device features a high-performance top Ge (110)/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\langle 110\rangle $ </tex-math></inline-formula> channel on a bottom Si CMOS. To ensure high performance without causing damage to the bottom Si n-FETs, the maximum thermal budget during the fabrication of the top Ge p-FETs was limited to 400 °C. We systematically investigated the mobility enhancement of the thin Ge (110) nanosheet (NS) channel p-FETs as a function of channel orientation. Our results demonstrate that the low effective hole mass along the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\langle 110\rangle $ </tex-math></inline-formula> direction on Ge (110) wafer provides record-high mobility of 400 cm2/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}\cdot \text{s}$ </tex-math></inline-formula> (corresponding to 760 cm2/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}\cdot \text{s}$ </tex-math></inline-formula> when normalized by footprint) at room temperature, which is the highest reported among the Ge p-FETs with similar channel thicknesses.