A 78.8fJ/b/mm 12.0Gb/s/Wire Capacitively Driven On-Chip Link Over 5.6mm with an FFE-Combined Ground-Forcing Biasing Technique for DRAM Global Bus Line in 65nm CMOS
Sang‐Yoon Lee, Jaekwang Yun, Suhwan Kim
Abstract
Advances in virtual reality, artificial intelligence, and big data have increased demand for high-bandwidth memory. Accordingly, pre-fetch sizes have also increased with DRAM generations, meaning an increased number of global bus lines. An increase to this number is limited as it also increases the chip size; instead, the data-rate per lane can be increased for higher throughput [1]. As the global bus lines are on-chip wires in a DRAM chip, they can be driven capacitively. Prior work [2], [3] has shown the superior efficiency of capacitive drivers, over conventional repeaters, in driving on-chip wires at the cost of a reduced voltage swing. However, as there is no well-defined DC level on the capacitively-driven wires [4], wire biasing is fraught with implementation challenges [3]. To define the DC potential on the interconnect, prior work sent signals differentially [2], [4], [5] or dissipated static power to define the DC level [3]. Unfortunately, these approaches may not be preferable for DRAM chips that require dense and energy-efficient data transfers.