Stable High Temperature Operation of p-GaN Gate HEMT With Etch-Stop Layer
Hanwool Lee, Hojoon Ryu, Junzhe Kang, Wenjuan Zhu
Abstract
High-temperature operation of the p-GaN gate high-electron-mobility transistor (HEMT) was investigated, specifically up to 500 °C. The p-GaN gate HEMT demonstrated stable behavior with normally-off operation, steep increase of drain current in the subthreshold region, and suppressed off-state current. By adding Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> etch-stop layer, the device showed significant reduction in subthreshold swing when measured at 500 °C, effectively mitigating hysteresis in the transfer characteristics. Additionally, the lifetime of the gate stack with the etch-stop layer was estimated to be much longer than that of the stack without the etch-stop layer. Through the integration of the depletion-mode (D-mode) metal-insulator-semiconductor HEMT (MIS-HEMT) device with the p-GaN gate device, a direct-coupled field-effect transistor logic (DCFL) inverter was fabricated. This inverter showed stable logic operation up to 500 °C, featuring rail-to-rail operation and large gain. A long-term reliability test conducted at 500 °C for 100 hours revealed stabilized on-state and off-state values after about 50 hours of operation.