Frequency Multiplier-by-4 (Quadrupler) with 52 dB Spurious-Free Dynamic Range for 152 GHz to 220 GHz (G-Band) in 130 nm SiGe
Paul Stärke, Vincent Ries, Corrado Carta, Frank Ellinger
Abstract
This work presents a frequency multiplier-by-4, which uses extensive passive filtering to improve the rejection of the undesired harmonics and increase the spurious-free dynamic range (SFDR). The circuit is intended for mm-wave communication systems operating at 180 GHz and its active core consists of two push-push doubler stages and a two-stage output buffer. It achieves a bandwidth of 68 GHz, covering almost the complete G-band and exhibits an SFDR between 52 dBc and 64 dBc. The saturated output power is up to -1 dBm and the corresponding maximum dc power consumption is 45 mW, resulting in a dc efficiency of up to 1.8 %. The final chip occupies an area of 1.3 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and is implemented in a 130 nm SiGe BiCMOS process, which offers a maximum oscillation frequency f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> of 450 GHz. To the knowledge of the authors, this circuit offers the highest SFDR and one of the largest bandwidths of any fully-integrated mm-wave multiplier of factor 4 or above. The fabricated chip is also packaged into a waveguide module, which shows almost the same bandwidth and only 1 dB of additional loss at the output.