The lpGBT PLL and CDR Architecture, Performance and SEE Robustness
Stefan Biereigel, S. Kulis, R. Francisco, Pedro Leitao, Paul Leroux, P. Moreira, Jeffrey Prinzie
Abstract
We present the design, architecture and experimental results of the low jitter Clock and Data Recovery (CDR) and Phase Locked Loop (PLL) circuit in the Low-Power Gigabit Transceiver (lpGBT) ASIC. This circuit includes a low noise radiation-tolerant integrated LC-oscillator with a nominal frequency of 5.12 GHz to support a 10.24 Gbps uplink and a 2.56 Gbps downlink CDR. This CDR employs a novel loop architecture with a high-speed feed forward loop stabilization technique. A test circuit was fabricated in a 65 nm CMOS technology and has been tested experimentally for correct operation in the foreseen radiation environment.
Topics & Concepts
Phase-locked loopJitterCMOSTransceiverApplication-specific integrated circuitRobustness (evolution)Computer scienceElectronic engineeringPhase noiseTelecommunications linkDelay-locked loopComputer hardwareEngineeringTelecommunicationsChemistryGeneBiochemistryAdvancements in PLL and VCO TechnologiesRadio Frequency Integrated Circuit DesignElectromagnetic Compatibility and Noise Suppression