An Adaptive Lockstep Architecture for Mixed-Criticality Systems
Fabian Kempf, Thomas Hartmann, S. Baehr, Juergen Becker
Abstract
Software with different criticality levels. Currently, research mostly focuses on software aspects for those systems and disregards hardware aspects as well as fault tolerance. In this paper, we propose and investigate a novel processor architecture for adaptive fault tolerance. This is achieved by an adaptive lockstep architecture, where non-critical software is executed in a performance mode and critical software in a lockstep processor configuration. The program code runs on both processor cores when software is executed in performance mode. While in lockstep mode both processor pipelines appear as one to the software. Switching between both modes happens seamlessly and neither software interrupt nor processor reset is required. Our concept of an adaptive lockstep architecture is demonstrated by extending the Cobham Gaisler’s LEON3 processor. The evaluation shows a reasonable hardware overhead as well as a minimal runtime overhead due to the additional pipeline stage.