4.1 A 16GHz, $41\text{kHz}_{\text{rms}}$ Frequency Error, Background-Calibrated, Duty-Cycled FMCW Charge-Pump PLL
Pratap Tumkur Renukaswamy, Kristof Vaesen, Nereo Markulić, Veerle Derudder, Dae‐Woong Park, Piet Wambacq, Jan Craninckx
Abstract
FMCW radars are the key components for contactless range and motion sensing in industrial and healthcare applications. The radar-sensor performance, such as chirp bandwidth <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\text{BW}_{\mathrm{c}\text{hi}\text{rp}})$</tex> , chirp slope, and frequency-modulation (FM) linearity, are determined by the FMCW chirp generator. When battery powered, the radar should be able to operate in a duty-cycled mode with minimal overhead, i.e., fast startup, fast lock at the start of every chirp burst, and minimal reset time in-between chirps, without degrading the radar range and Doppler performance. This work presents a robust fast-lock-acquisition charge-pump (CP)-PLL with a PFO for duty-cycled chirp generation. A fractional-N CP-PLL in a two-point-modulation (TPM) architecture breaks the trade-off between the PLL bandwidth and fast-chirp synthesis [1], [2]. A time-domain sign-extraction by using a 1 b TOC [3] enables the background calibration. A phase-offset-compensating digital-to-time converter (POC-OTC) assists the sign-extraction by compensating the positive/negative phase offsets generated within the type-Il PLL loop.