Scalability of Quad Interface p-MTJ for 1X nm STT-MRAM With 10-ns Low Power Write Operation, 10 Years Retention and Endurance > 10¹¹
S. Miura, K. Nishioka, Hiroshi Naganuma, T. V. A. Nguyen, H. Honjo, Shoji Ikeda, Toshinari Watanabe, Hirofumi Inoue, M. Niwa, Takaho Tanigawa, Y. Noguchi, Toru Yoshizuka, M. Yasuhira, Tetsuo Endoh
Abstract
We fabricated a quadruple-interface perpendicular magnetic tunnel junction (MTJ) (Quad-MTJ) down to 33 nm using physical vapor-deposition, reactive ion etching, and damage-control integration process technologies that we developed under a 300-mm process. We demonstrated the greater scalability and higher writing speed of Quad-MTJ compared with double-interface perpendicular MTJ: 1) it has twice the thermal stability factor-1X nm Quad-MTJ can achieve 10 years retention-while maintaining a low resistance-area product and high tunnel magnetoresistance ratio; 2) smaller overdrive ratio of write voltage to obtain a sufficiently low write-error rate; 2) smaller pulsewidth dependence of the switching current; and 4) more than double the write efficiency at 10-ns write operation down to 33-nm MTJ. The effective suppression of the switching current increase for higher write speeds was explained by the spin-transfer-torque model using the Fokker-Planck equation. Our 33-nm Quad-MTJ also achieved excellent endurance (at least 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> ) owing to its higher write efficiency and low-damage integration-process technology. It is thus a promising method for low power, high speed, and reliable STT-MRAM with excellent scalability down to the 1X nm node.