A Fully-Synthesizable Fractional-N Injection-Locked PLL for Digital Clocking with Triangle/Sawtooth Spread-Spectrum Modulation Capability in 5-nm CMOS
Bangan Liu, Yuncheng Zhang, Junjun Qiu, Hóngyè Huáng, Zheng Sun, Dingxin Xu, Haosheng Zhang, Yun Wang, Jian Pang, Zheng Li, Xi Fu, Atsushi Shirane, Hitoshi Kurosu, Yoshinori Nakane, Shunichiro Masaki, Kenichi Okada
Abstract
A fully synthesizable injection-locked phase-locked loop (IL-PLL) for digital clocking is proposed in this letter. The phase-locked loop (PLL) is implemented in a 5-nm CMOS process, with only digital standard cells are used. With proposed triple-path operation and digital offset control for digital-to-time converter (DTC), low-jitter fractional-N frequency synthesis, and highly-linear spread-spectrum clocking are realized with low-power consumption. The PLL core area is 0.0036 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . With 100-MHz reference frequency, better than -234.7 dB figure-of-merit (FOM) is achieved in the fractional-N mode, with -44.3 dBc worst-case fractional spur. The proposed PLL has the smallest chip area, highest FOM, and lowest fractional spur among ring oscillator (RO)-based fractional-N PLLs in sub-20-nm processes.