Analog Layout Placement for FinFET Technology Using Reinforcement Learning
Mehrnaz Ahmadi, Lihong Zhang
Abstract
Despite all efforts being made to ease analog layout generation, the designers' expertise is still highly demanded in the process of analog IC physical design. Recently, some endeavors started to leverage artificial intelligence (AI) to tackle the complexity of analog layout optimization and alleviate the high demand for the designers' experience in the design process. However, these methods, which mainly rely on using the previous designs, are not effective to the unseen data (or scenarios) that were not included in the AI training. In this paper, we have proposed a reinforcement-learning-based method that can fully automate analog layout placement optimization. It is not only applicable to any unseen analog placement scenarios, but also can meet the requirements of analog layout placement designs in the advanced FinFET technology. Our experimental results show that the proposed method can place analog modules subject to the defined objectives 77x faster than the conventional analytical methods (e.g., conjugate gradient) without compromising the optimization accuracy.