16.6 An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter
Hajime Shibata, Gerry Taylor, Bob Schell, Victor Kozlov, Sharvil Patil, Donald Paterson, Asha Ganesan, Yunzhi Dong, Wenhua Yang, Yue Yin, Zhao Li, Prawal Shrestha, Athreya Gopal, Aathreya S. Bhat, Shanthi Pavan
Abstract
Modern wireless communication systems operating at tens of GHz have opened a near-GHz contiguous RF BW for various applications. Further, spectral efficiency has often necessitated such applications to use MIMO and beamforming, resulting in systems that are highly integrated and require tight power budgets. The ADC, being an indispensable element of these systems, has been thus pushed to digitize ever-increasing BWs (>500MHz) with low power dissipation and area, in an integration-friendly manner. Continuous-time (CT) ΔΣ ADCs have traditionally been used in integrated receiver applications because their oversampling and inherent anti-aliasing ease the frequency planning and make on-chip active filtering possible. Designing these CT ΔΣ ADCs for BW specifications of more than 500MHz, however, is challenging. Digitizing near-GHz RF BW with a typical oversampling ratio (OSR) of ~16 requires a very high sampling frequency with prohibitive power dissipation even in advanced process nodes. Using discrete-time (DT) ADCs is a possibility, but the ADC will still need to be oversampled to ease on-chip filtering and to prevent unwanted mixer terms from aliasing in-band. Thus, the power consumption and area penalties can be prohibitive.