A 650-pW, 205 °C Temperature Range Voltage Reference With Curvature-Based Temperature and BJT-Enhanced Process Compensation Techniques
Cheng-Ze Shao, I-Fan Lin, Yu‐Te Liao
Abstract
This letter presents a 650-pW 1-V hybrid voltage reference (VR) with curvature-based temperature compensation and self-biasing feedback loop (SBFL) in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol{\mu }\text{m}$ </tex-math></inline-formula> CMOS process. The stacked-diode-MOS-transistor (SDMT) architecture with SBFL improves the startup time and independence with regard to the supply voltage. The curvature compensation extends the temperature range by adjusting the current ratio in the top and downside transistor of the SDMT VR. A stacked bipolar junction transistor (BJT) is used to compensate for the MOS transistor gate-source voltage variations. The design achieves a 45 ppm/°C from −55°C to 150°C, a line sensitivity of 0.016%/V, and a power supply rejection ratio (PSRR) of −71 dB at 100 Hz.