Shortening the gap between pre- and post-layout analog IC performance by reducing the LDE-induced variations with multi-objective simulated quantum annealing
Ricardo Martins, Nuno Lourenço, Ricardo Póvoa, Nuno Horta
Topics & Concepts
Computer scienceFloorplanSimulated annealingIntegrated circuit layoutPhysical designIC layout editorIntegrated circuitElectronic circuitDesign flowPlacementMixed-signal integrated circuitDesign layout recordAnalogue electronicsProcess (computing)Electronic engineeringCircuit designCircuit extractionVoltageAlgorithmEmbedded systemElectrical engineeringEquivalent circuitOperating systemEngineeringVLSI and FPGA Design TechniquesAdvancements in Photolithography TechniquesAdvancements in Semiconductor Devices and Circuit Design